The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a bipolar transistor and a method for fabricating the same.
FIG. 1 shows a cross-sectional view of a heterojunction bipolar transistor formed using a compound semiconductor. Its fabrication process will be explained below.
First of all, an n+ GaAs subcollector layer 12, n- GaAs collector layer 13, p+ GaAs base layer 14, n- GaAs emitter layer 15, and n+ GaAs emitter cap layer 16 are sequentially grown on a GaAs substrate 11 through epitaxy. Then, a metal is deposited thereon and patterned to form an emitter electrode 17. The emitter cap layer 16 and the emitter layer 15 are patterned to form an emitter portion.
Thereafter, a metal is deposited on the exposed base layer 14 to form a base electrode 18 and the base layer 14 is patterned to form a base portion. At the same time, the collector layer 13 is etched. Then a metal is deposited on the exposed subcollector layer 12 and patterned to form a collector electrode 19. The subcollector layer 12 is etched to form a collector portion.
For increasing the operation speed of the semiconductor device, it is required that the base layer be thin and the emitter area be small. However, in the aforementioned conventional method, a narrow space is formed between the emitter electrode 17 and base electrode 18 and a thin base layer is formed. Thus, the base layer may be easily damaged during etching of the emitter layer. This makes the fabrication process difficult.
In order to solve the above problem, a technique using selective epitaxy has been proposed. This technique will be explained below with reference to FIG. 2.
As shown in FIG. 2, a subcollector layer 12, a collector layer 13 and a base layer 14 are sequentially formed on a substrate 11 through epitaxy. An epitaxy mask is formed of Si.sub.3 N.sub.4 on the portion where a base is to be formed, and then the epitaxy is carried out. Accordingly, a selective epitaxy is accomplished to thereby grow an emitter layer 15 and an emitter cap layer 16 on the portion where the epitaxy mask (Si.sub.3 N.sub.4) is not formed. That is, the emitter layer 15 and emitter cap layer 16 are not grown on the epitaxy mask. Here, the emitter layer 15 and emitter cap layer 16 are formed in the shape of an overhang around the epitaxy mask as shown in FIG. 2.
Thereafter, the epitaxy mask is etched, and a metal layer is deposited thereon. By doing so, an emitter electrode 17 and a base electrode 18 are simultaneously formed using the overhang. Then, the portion of the metal layer formed where the base electrode 18 is not formed is etched through photolithography. The base layer 14 and collector layer 13 are also selectively etched through photolithography. Then a collector electrode 19 is formed on the exposed subcollector layer 12.
According to this technique, the emitter electrode 17 and base electrode 18 are simultaneously formed, and the collector electrode 19 is formed on the exposed subcollector layer 12. If the emitter electrode 17 and base electrode 18 cannot be formed using the same metal material, the emitter electrode 17 is formed first before the epitaxy mask is etched. Then the epitaxy mask is etched and the base electrode 18 is formed by depositing a metal on portions of the base layer 14.
In the aforementioned method for fabricating the bipolar transistor as shown in FIG. 2, which attempts to solve the problems of the device shown in FIG. 1, the base layer 14 is grown by a first selective epitaxy, and the emitter layer 15 and emitter cap layer 16 are grown by a second selective epitaxy using a Si.sub.3 N.sub.4 layer as an epitaxy mask. This technique has the following advantages. Only the Si.sub.3 N.sub.4 mask layer is removed in order to form the base electrode 18, and the emitter electrode 17 and base electrode 18 can be simultaneously formed using the overhang of the emitter layer 15.
In the aforementioned technique, however, the emitter-base junction, which is an important portion of the bipolar transistor, is exposed during the fabrication process, which results in a deterioration of junction characteristics. Also, two-time epitaxy must be carried out complicating the fabrication process. Furthermore, although the surface area of the emitter layer 16 can be decreased, the surface area of the emitter electrode 17 and emitter layer 16 becomes identical. Thus, if the surface area of the emitter layer 16 is small, the surface area of the emitter electrode 17 becomes small, which makes it difficult to connect the emitter electrode 17 to a pad, or to another electrode.